Concepts of high level synthesis using SystemC

Authors

  • K. Pakalniškis Kaunas University of Technology
  • E. Kazanavičius Kaunas University of Technology

Abstract

The paper shows the concepts of high level synthesis with SystemC. One important aspect of using SystemC classes is that you can use the same environment for all steps in the synthesis flow. This concept makes the unified system design methodology starting from functional verification to synthesis and architectural verification.

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Published

2002-08-28

Issue

Vol. 43 No. 2 (2002)

Section

SIGNAL PROCESSING

License

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